The present invention relates generally to non-volatile memory devices and in particular the present invention relates to a synchronous non-volatile flash memory.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCS have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array which includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM""s can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a manner similar to SDRAM operation.
The above mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a synchronous non-volatile memory comprises an array of non-volatile memory cells, a control circuitry, and a non-volatile mode register having a plurality of bit locations to store mode data. The control circuitry establishes operating settings in response to the mode data.
In another embodiment, a synchronous non-volatile memory comprises an array of non-volatile memory cells, control circuitry, a non-volatile mode register having a plurality of bit locations to store mode data, and a volatile mode register coupled to the non-volatile mode register to receive a copy of the mode data. The control circuitry is coupled to the volatile mode register such that the control circuitry establishes operating settings in response to the mode data stored in the volatile mode register.
A method of operating a synchronous non-volatile memory device is provided. The method comprises programming a non-volatile mode register with mode data, initiating a data access operation, reading the mode data, and controlling the data access operation in response to the mode data.
Another method of operating a synchronous non-volatile memory device comprises programming a non-volatile mode register with mode data, providing power to the memory device, copying the mode data from the non-volatile to a volatile mode register, initiating a data access operation, reading the mode data from the volatile mode register, and controlling the data access operation in response to the mode data.